WSURF Case 844
Low Power 16-bit Analog-to-Digital Converter
Summary
WSU researchers have developed a low-power, 16-bit, 500 kS/s analog-to-digital converter (ADC). The ADC can operate with +/- 1.5 V supply voltages, in a charge redistribution, self-calibrating, successive approximation design. This design enables power dissipation to be reduced by a factor of 2 (ex. 6.2 mW for +/- 1.5 V input supplies).
A novel interleaving architecture and an improved comparator design contribute to reducing the power while maintaining high accuracy and speed. This ADC was developed to digitize the amplified signals from a 16-channel low noise sensor IC.
Applications & Advantages
This ADC design includes the following:
- 16 bit resolution
- Low power input
- 15 bit accuracy at 500kS/s
- Low signal-to-noise ratio
- Low power dissipation
IP Status
US patent pending. Available for license.
For more information about this technology please contact WSURF:
1610 NE Eastgate Blvd, Suite 650
Pullman, WA 99164
Phone: (509) 335-5526
Fax: (509) 335-7237
wsurf@wsu.edu
